AMD Athlon XP 1800+
Monday, October 22, 2001
As you may have noticed from reading the bottom table on the preceding page, the Athlon XP is equipped with 384KB of on-chip cache - 128K of L1 (64K instructions, 64K data), and 256K of L2 cache. Obviously, the Palomino core is demonstrating new in this regard.
What does separate the Palomino core from its predecessors is the combination of the "QuantiSpeed Architecture", a significant reduction in power consumption & heat dissipation, an integrated thermal diode, a physical base constructed of a new material, and support for SSE instructions.
QuantiSpeed Architecture
The Athlon XP's "Quantispeed" architecture is actually a set of four different technologies that have been added to the Palomino core. They are:
Exclusive and speculative Translation Look-aside Buffers (TLBs)
A fully pipelined, super-scalar Floating-Point Unit (FPU)
A 9-issue, fully-pipelined, superscalar microaritecture
Hardware data prefetch
Exclusive and speculative Translation Look-aside Buffers
The Palomino's TLBs are some of its best implemented structures. Their presence is a bit similar to having a level of cache in addition to the L1 and L2. The TLB structures in QuantiSpeed Architecture keep the maps to critical data and instructions close to the processor. These structures are designed to prevent the processor from stalling or waiting when future data and/or instructions are requested. The Palomino core's TLBs are improvements over previous implementations for three reasons. First, the TLB structures are now larger, and allow the AMD Athlon XP to access to additional maps. Second the exclusive nature of these structures removes the duplication of information, freeing- up more space in the Level 2 cache for other useful information to be used by the processor. Third, their speculative nature allows the AMD Athlon XP processor to generate future maps of critical data and instructions quickly.
Fully pipelined, superscalar floating-point unit (FPU)
This particular technology isn't exactly new, since it's long been part of AMD's "Thunderbird" and "Duron" processors, but mentioning it does highlight the formidable number-crunching abilities of the Athlon.
9-issue, fully-pipelined superscalar mircoarchitecture
This technology represents AMD's vision for the optimization of their CPUs. As the we all know, the longer a pipeline is, the fewer the instructions it can process per cycle, but the greater the potential clock-frequency.
On the other hand, shorter pipelines can execute more instructions per colock cycle, but have a lower clock-frequency ceiling.
AMD, for its part, has optimized the length of the XP's pipeline in order to maximize the number of instructions that can be executed per cycle (expressed as IPC, or instructions per cycle), while obtaining an optimal operating frequency.
Hardware data prefetch
This technology, also used in the Intel Pentium 4, consists of a mechanism which observes and fetches commonly used data from main memory, and stores it in the L1 cache. This is an excellent way to optimize processor performance by evading data the need to wait for while critical instructions are called-up from the main memory sub-system. Its greatest feature, though, has to be the fact that applications such as games and office programs don't have to be coded to take full advantage of hardware prefetch's benefits.
Next: The Power Rating and the performance myth
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